TOMMY’S PHYSICAL DESIGN ACADEMY

Build a chip, one stage at a time.

Learn the concept, watch the animated explanation, then solve a scored engineering challenge.

12interactive modules

FIRST TIME HERE?

Start with pictures, not a wall of terminology.

Explore seven core ideas through labeled diagrams, adjustable examples, and concept checks before trying the scored labs below. Learn what changes, why it matters, and what a simplified model cannot tell you.

Start the visual walkthrough

New to digital logic? Begin with VLSI Basics. The module order is a learning path, not a rigid tool flow: power and timing work span multiple stages.

01

FOUNDATION

Chip Floorplanning

Balance macros, I/O, blockages, halos, channels, and wirelength.

Drag & dropCongestion
Launch module → 02

OPTIMIZATION

Standard-Cell Placement

Place connected cells into legal rows while controlling density and HPWL.

RowsHPWL
Launch module → 03

RELIABILITY

Power Planning

Build a strap network that reaches hotspots without exhausting metal resources.

IR dropStraps
Launch module → 04

SYNCHRONIZATION

Clock-Tree Synthesis

Insert clock buffers and balance arrival time across sequential sinks.

SkewLatency
Launch module → 05

CONNECTIVITY

Signal Routing

Route through a constrained grid while avoiding blockages and detours.

TracksDRC
Launch module → 06

PERFORMANCE

Timing Closure

Choose optimization actions that fix setup and hold within a power budget.

SlackECO
Launch module → 07

FINAL CHECK

Signoff Challenge

Diagnose DRC, antenna, timing, and power-integrity violations before tape-out.

DiagnosisTape-out
Launch module → 08

DESIGN METHODOLOGY

Hierarchical Design Flow

Partition a large chip into manageable blocks while controlling interfaces and top-level crossings.

PartitioningIntegration
Launch module → 09

HIERARCHICAL TIMING

Block Timing Budgeting

Distribute a chip-level timing requirement across block delays and global interconnect margin.

I/O delaysMargin
Launch module → 10

ANALYSIS FLOW

STA with EDA Tools

Assemble the required design data, constraints, analysis conditions, checks, and reports.

SDC/SPEFReports
Launch module → 11

PHYSICAL CONSTRAINTS

Blockage Engineering

Choose placement, halo, density, and layer-specific routing restrictions for real scenarios.

PlacementRouting
Launch module → 12

DESIGN DATA

DEF Explorer

Connect physical-layout information to DIEAREA, COMPONENTS, PINS, NETS, and other DEF sections.

LEF/DEFData model
Launch module →