PHYSICAL DESIGN LAB · MODULE 01

Floorplan Forge

Course map Visual explanation

Interactive canvas

Core area · 1000 × 700 μm

Planning
Chip floorplanning game canvas Drag macros inside the chip core while avoiding overlaps and a central placement blockage. HARD BLOCKAGE NO CELL OR MACRO PLACEMENT CHIP INPUT DDR DATA CHIP OUTPUT PCIe TX
Drag a macro to begin
TOMMY · LIVE GUIDE

I’ll analyze every move. Start by dragging a macro connected by a thick orange fly-line.

QUICK TUTORIAL

Think like a floorplanner

  1. Drag macros into the outlined core area.
  2. Follow the fly-lines: shorter lines mean shorter wires.
  3. Avoid red states: they indicate overlap or blockage violations.
  4. Watch the score and satisfy all three objectives.